Program Partitioning and Scheduling for Scalable Parallel Machines

In this work, the issue of regeneration of the schedule for a set of scalable distributed memory architectures with diierent communication costs has been addressed. A new concept of dominant edges of a schedule has been introduced to denote those edges which dictate schedule regeneration due to the changes in their communication costs. It is shown that under certain conditions, schedule on the whole or at least part of the graph can be reused for a diierent architecture by meeting both the feasibility and the optimality conditions stated above. Usefulness of this method has been demonstrated by incorporating it in the scheduler of the compiler backend for targeting Sisal(Streams and Iterations in a Single Assignment Language) on a family of Intel i860 architectures : Gamma, Delta and Paragon which vary in their communication costs. It is shown that as high as 65 % of the schedule could be re-used thereby avoiding program re-partitioning and scheduling.